ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES

PURPOSE: An enabling an integrated memory controller is provided to improve the whole performance by applying a lower refresh rate than a predetermined refresh rate which is defined by a memory module. CONSTITUTION: A system(100) comprises an integrated circuit(102), a DRAM sub system(104), and a me...

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Bibliographic Details
Main Authors KUMAR MOHAN J, NATU MAHESH S, DATTA SHAMANNA M, ALEXANDER JAMES W, KHANNA RAHUL
Format Patent
LanguageEnglish
Korean
Published 08.07.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE: An enabling an integrated memory controller is provided to improve the whole performance by applying a lower refresh rate than a predetermined refresh rate which is defined by a memory module. CONSTITUTION: A system(100) comprises an integrated circuit(102), a DRAM sub system(104), and a memory(106). The integrated circuit comprises a logic controlling the transmission of information to the DRAM sub system. The integrated circuit comprises a processor cores and a logic unit(110). The process core is comprised of one of general process cores and an integrated process cores with graphic processor cores.
Bibliography:Application Number: KR20090129726