TEST METHOD OF FLASH MEMORY DEVICE
PURPOSE: A test method of a flash memory device is provided to reduce a column leakage due to overstress by erasing over-erased cells having a damage tunnel oxide film to be normal. CONSTITUTION: A photoresist pattern defining an element isolation film is formed on a semiconductor substrate(20). The...
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Main Author | |
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Format | Patent |
Language | English Korean |
Published |
08.07.2010
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Subjects | |
Online Access | Get full text |
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Summary: | PURPOSE: A test method of a flash memory device is provided to reduce a column leakage due to overstress by erasing over-erased cells having a damage tunnel oxide film to be normal. CONSTITUTION: A photoresist pattern defining an element isolation film is formed on a semiconductor substrate(20). The element isolation film(26) is formed on a substrate. A P well and N well are formed on the semiconductor substrate. A floating gate(28) is formed by evaporating a first polysilicon layer in a cell region. An oxide-nitride-oxide film(29) is formed on the floating gate of the cell region. A control gate(30a) and a gate(30b) are formed in the cell region and peripheral area. A spacer(32) is formed in a control gate and both sides of the gate. An interlayer insulating film(34) is formed on the semiconductor substrate. |
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Bibliography: | Application Number: KR20080138809 |