MANUFACTURING METHOD OF GATE PATTERN FOR NONVOLATILE MEMORY DEVICE

PURPOSE: A gate patterning method of a non-volatile memory element is provided to remove voids and seams created inside a first conductive film by additionally etching the top of a first conductive film after forming the first conductive film between element isolation films. CONSTITUTION: An element...

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Bibliographic Details
Main Author JIN, GYU AN
Format Patent
LanguageEnglish
Korean
Published 06.07.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A gate patterning method of a non-volatile memory element is provided to remove voids and seams created inside a first conductive film by additionally etching the top of a first conductive film after forming the first conductive film between element isolation films. CONSTITUTION: An element isolation film(111a) higher than the surface of the semiconductor substrate is formed inside the trench of a semiconductor substrate(101). A gate insulating layer(113) is formed on the top of the semiconductor substrate between the element isolation films. A first conductive film(115) filling the space between the element isolation films on the top of the gate insulating layer is formed. The first conductive film is etched so that the height of the first conductive is lower than the height of the element isolation film. The second conductive film filling the space between the element isolation films is formed on the top of the first conductive film.
Bibliography:Application Number: KR20080134340