STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

PURPOSE: A stacked semiconductor package and a method for manufacturing the same are provided to reduce the failure due to the bending of a semiconductor chip by attaching the semiconductor chip of which size is smaller than a wafer with a base substrate and a reinforce material. CONSTITUTION: First...

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Bibliographic Details
Main Author CHUNG, QWAN HO
Format Patent
LanguageEnglish
Korean
Published 16.04.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A stacked semiconductor package and a method for manufacturing the same are provided to reduce the failure due to the bending of a semiconductor chip by attaching the semiconductor chip of which size is smaller than a wafer with a base substrate and a reinforce material. CONSTITUTION: First semiconductor chips(10) include a first through electrode(30). The first through electrode is formed in a first blind via which passes through a first bonding pad on the first semiconductor chip. The upper side of the first semiconductor chips is arranged on a base substrate(70). The space between the first semiconductor chips are filled in order to form a reinforce material. The first through electrode is protruded from the lower side of the first semiconductor chips. An adhesive material(50) which exposes the first through electrode is arranged on the lower side of the first semiconductor chips. Second semiconductor chips(20) are arranged on the adhesive material.
Bibliography:Application Number: KR20080098761