METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE

PURPOSE: A method for manufacturing a semiconductor package is provided to reduce a manufacturing cost of the semiconductor package by forming a via pattern for electrical connection with a printing method and a plating process instead of a bump. CONSTITUTION: An insulation layer(110) is attached on...

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Bibliographic Details
Main Author JUNG, YOUNG HY
Format Patent
LanguageEnglish
Published 07.01.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A method for manufacturing a semiconductor package is provided to reduce a manufacturing cost of the semiconductor package by forming a via pattern for electrical connection with a printing method and a plating process instead of a bump. CONSTITUTION: An insulation layer(110) is attached on a semiconductor chip with a plurality of bonding pads(102). The insulation layer includes via holes exposing the bonding pad. A via pattern is formed in the exposed via holes. The semiconductor chip with the via patterns is attached on the upper side of the substrate with a plurality of connection pads to be connected to the connection pad corresponding to the via pattern.
Bibliography:Application Number: KR20080062919