PHASE-CHANGE RANDOM ACCESS MEMORY CAPABLE OF PREVENTING COUPLING NOISE DURING READ WHILE WRITE OPERATION

A phase change memory device is provided to minimize a coupling noise by arranging a shielding unit between a write global bit line and a read global bit line. Local bit lines(LBL0-LBL7) are connected to memory cells(SCA). One or more write global bit lines(WGBL) are connected to the local bit lines...

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Bibliographic Details
Main Authors CHOI, BYUNG GIL, CHO, BEAK HYUNG
Format Patent
LanguageEnglish
Published 26.08.2009
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A phase change memory device is provided to minimize a coupling noise by arranging a shielding unit between a write global bit line and a read global bit line. Local bit lines(LBL0-LBL7) are connected to memory cells(SCA). One or more write global bit lines(WGBL) are connected to the local bit lines. One or more read global bits(RGBL) line are connected to the local bit lines. A plurality of banks are formed with a stack structure. A shielding unit is arranged between the adjacent write global bit line and the read global bit line. A ground voltage is applied to the shielding unit.
Bibliography:Application Number: KR20080015918