METHOD OF FORMING NANOWIRE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING NANOWIRE

• Main Authors: JEON JOONG S, BAE, EUN JU, KIM, JUN YOUN
• Format: Patent
• Language: English
• Published: 25.03.2009
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT THEREOF; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS,MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES ASDISCRETE UNITS; NANOTECHNOLOGY; PERFORMING OPERATIONS; SEMICONDUCTOR DEVICES; SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS; TRANSPORTING

A nanowire formation method is provided to control easily size and forming location of nanowire and not to move Nanowire to another substrate in order to manufacture semiconductor device. A nanowire formation method comprises steps of: forming SiyGe1-y layer patterned on base layer; performing oxidation process for the patterned SiyGe1-y layer; and forming the oxide layer and nanowire. The step of forming the patterned SiyGe1-y layer includes steps of: preparing lamination structure comprising an insulating layer(10), an Si layer(20) and an SixGe1-x layer(SG1); diversifying the Si layer to the SiyGe1-y layer by performing the oxidation process for the SixGe1-x layer; and patterning the SiyGe1-y layer.