ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

• Main Authors: AHN, TAE JOON, KANG, SU HYUK
• Format: Patent
• Language: English
• Published: 25.09.2008
• Subjects: BASIC ELECTRIC ELEMENTS; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; SEMICONDUCTOR DEVICES; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

An array substrate for an LCD(Liquid Crystal Display) and a method for manufacturing the same are provided to constitute a thin film transistor where a semiconductor is formed of a poly-silicon layer crystallized through alternating magnetic field crystallization, thereby improving the electron mobility of the thin film transistor. A first gate line(202) and a first gate electrode(203) is formed on a substrate(201) by using a first conductive layer of a first metal material. A second gate line(206) and a second gate electrode(207) are formed to wrap the first gate line and the first gate electrode, respectively, by using a second conductive layer of a second metal material having a larger melting point than the first metal material. A gate-insulating layer(211) is formed on the second gate line and the second gate electrode. A first intrinsic amorphous silicon layer of a firs thickness is formed on the gate-insulating layer. The first intrinsic amorphous silicon layer is crystallized into a poly-silicon layer(213) under a first temperature ambience. A second intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer, and a metal layer are sequentially formed on the poly-silicon layer, and then pattern-etched to form a data line crossing the gate line, a three-layered semiconductor pattern, and source and drain electrodes. A passivation layer is formed on the data line, and the source and drain electrodes, wherein the passivation layer partially exposes the drain electrode. A pixel electrode is formed on the passivation layer, wherein the pixel electrode is contacted with the drain electrode.