APPARATUS AND METHOD FOR ELIMINATING ERRORS IN A SYSTEM HAVING AT LEAST TWO EXECUTION UNITS WITH REGISTERS

An apparatus (120) for eliminating errors in a system (100, 400) having at least two execution units (101, 102) with registers is presented, wherein the registers are designed to hold data. The apparatus has comparison means (126) which are set up in such a manner that a discrepancy and thus an erro...

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Bibliographic Details
Main Authors KOTTKE THOMAS, LINDENKREUZ THOMAS, BOEHL EBERHARD, HARTER WERNER, TUMMELTSHAMMER PETER
Format Patent
LanguageEnglish
Published 23.07.2008
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An apparatus (120) for eliminating errors in a system (100, 400) having at least two execution units (101, 102) with registers is presented, wherein the registers are designed to hold data. The apparatus has comparison means (126) which are set up in such a manner that a discrepancy and thus an error can be determined by comparing data which are intended to be stored in the registers. At least one shadow register (121, 122), which is set up in such a manner that it can store data relating to data from the registers, and means for restoring error-free data in at least one register on the basis of the data in the at least one shadow register (121, 122) in the event of an error being determined are furthermore provided. This apparatus can be used to improve the reliability of a multi-core processor (100).
Bibliography:Application Number: KR20087011612