ALIGNMENT AND OVERLAY KEY OF SEMICONDUCTOR DEVICE AND METHOD OF THE SAME

An alignment and an overlay key structure of a semiconductor device and a forming method of the same are provided to obtain high reliability by stabilizing a manufacturing process. A semiconductor substrate(110) includes a first alignment key region(A) and a second alignment key region(B). A plurali...

Full description

Saved in:
Bibliographic Details
Main Authors YEO, GI SUNG, PARK, JOON SOO, KANG, HYUN JAE, HAM, BOO HYUN, CHOI, SUNG WON, CHO, HAN KU
Format Patent
LanguageEnglish
Published 16.07.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:An alignment and an overlay key structure of a semiconductor device and a forming method of the same are provided to obtain high reliability by stabilizing a manufacturing process. A semiconductor substrate(110) includes a first alignment key region(A) and a second alignment key region(B). A plurality of first alignment keys(113) are provided in the first alignment key region. An anti-growth layer(115a) is formed to cover the first alignment key region including the first alignment keys. An isolation layer pattern(114b) is provided in the second alignment key region. A plurality of second alignment keys(115b) are formed on the isolation layer pattern. The anti-growth layer includes polysilicon. The isolation layer pattern is formed to define a plurality of first dummy alignment keys.
Bibliography:Application Number: KR20070003845