SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREOF

• Main Author: SONG, YOON GYU
• Format: Patent
• Language: English
• Published: 15.01.2008
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A semiconductor memory device and an operation method thereof are provided to reduce test initialization time by performing hidden test operation using CBR(CAS Before RAS) refresh. A memory cell array(10) comprises a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines as writing data applied to the bit line or reading and outputting the data to the bit line. An address decoder selects at least one word line in response to a refresh address and selects all of the plurality of bit lines in response to a hidden write signal, when CBR(CAS Before RAS) refresh operation is requested in a test mode. A hidden write control circuit(34) generates the hidden write signal, when the CBR refresh operation is requested in the test mode. A refresh address generation circuit(30) generates the refresh address, when the CBR refresh operation is requested in the test mode. A data input circuit(54) applies the data to the plurality of bit lines, when the CBR refresh operation is requested in the test mode.