SYNCHRONOUS MEMORY DEVICE INCLUDING CIRCUIT FOR ADDRESS PIN REDUCTION SHARING ADDITIVE LATENCY STRUCTURE

• Main Authors: SUNG, HUI KYUNG, CHO, YOUNG CHUL
• Format: Patent
• Language: English
• Published: 29.11.2007
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A synchronous memory device comprising an address pin reduction circuit sharing an additive latency structure is provided to enable an AR test using a high speed internal clock, as sharing the additive latency structure used in the prior DDR2 synchronous memory device. A shift register(20) latches a plurality of addresses, buffered by an address buffer, in synchronize to a clock signal. An additive latency switch module selects more than one address among the plurality of addresses delayed by the shift register on the basis of an additive latency command, and connects the selected address to a column address line. An address pin reduction switch module selects more than one address among the plurality of addresses and the addresses delayed by the shift register on the basis of an address pin reduction command, and connects the selected address to a column address line and a row address line.