METHOD OF SEMICONDUCTOR FABRICATION INCORPORATING DISPOSABLE SPACER INTO ELEVATED SOURCE/DRAIN PROCESSING

• Main Authors: CHEN JIAN, ROSSOW MARC A, SHIHO YASUHITO, MORA RODE R
• Format: Patent
• Language: English
• Published: 16.01.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A semiconductor fabrication process includes forming a gate electrode (110) overlying a substrate (108). A first silicon nitride spacer (122) is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer (130) is then formed adjacent the offset spacer. An elevated source/drain structure (132), defined by the boundaries of the disposable spacer (122), is then formed epitaxially. The disposable spacer (130) is then removed to expose the substrate (108) proximal to the gate electrode (110) and a shallow implant, such as a halo (140) or extension implant (142), is introduced into the exposed substrate proximal the gate electrode. A replacement spacer (136) is formed substantially where the disposable spacer (130) existed and a source/drain implant (140) is done to introduce a source/drain impurity distribution into the elevated source drain (132). The gate electrode (110) may include an overlying silicon nitride capping layer (144) and the first silicon nitride spacer (122) may contact the capping layer (144) to surround the polysilicon gate electrode (110) in silicon nitride. ® KIPO & WIPO 2007