METHOD AND STRUCTURE FOR FABRICATING VERTICAL TRANSISTOR CELL AND TRANSISTOR CONTROL MEMORY CELL TO AVOID ACCUMULATION OF CHARGE CARRIERS AND FLOATING BODY PHENOMENON

• Main Authors: MANGER DIRK, GOEBEL BERND, SCHLOESSER TILL
• Format: Patent
• Language: English; Korean
• Published: 21.08.2004
• Edition: 7
• Subjects: ELECTRICITY

PURPOSE: A method for fabricating a vertical transistor cell is provided to prevent accumulation of charge carriers in an active region and a floating body phenomenon without increasing an area required by a transistor cell by making the active region adjacent to a transistor cell become a part of a main body of an adjacent layer and by connecting the active region and the main body of the adjacent layer with each other. CONSTITUTION: Vertical transistor cells(81) are disposed in a transistor cell array formed in a substrate, made of columns in the X-axis direction and rows in the Y-axis direction. A source/drain region(2) under the transistor cell is coupled to a common connection plate. A source/drain region(4) above the transistor cell comes in contact with a storage capacitor of a DRAM(dynamic random access memory) memory cell. An active trench(5) located between the transistor cells with wordlines(521) is formed along the X-axis direction. A gate electrode is partially formed by the wordlines. A conductive channel in the active region located between upper and lower source/drain junction regions is controlled by a voltage applied to the gate electrode.