SEMICONDUCTOR MEMORY DEVICE HAVING REFRESH CIRCUIT

PURPOSE: To secure stability of refresh operation in a semiconductor memory device in which refresh operation is performed without being instructed from the outside. CONSTITUTION: A refresh circuit 40 outputs a refresh command signal/REFE commanding execution of refresh operation. The refresh circui...

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Bibliographic Details
Main Authors TSUKUDE MASAKI, SATO HIROTOSHI, KOBAYASHI SHINICHI
Format Patent
LanguageEnglish
Korean
Published 29.01.2003
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE: To secure stability of refresh operation in a semiconductor memory device in which refresh operation is performed without being instructed from the outside. CONSTITUTION: A refresh circuit 40 outputs a refresh command signal/REFE commanding execution of refresh operation. The refresh circuit 40 includes a command signal activating circuit 50 activating the refresh command signal/ REFE and a determination circuit 60 determining whether an activated refresh command signal/REFE is to be outputted or not. The determination circuit 60 determines that the refresh command signal/REFE is outputted when the semiconductor memory device is in a standby state. 리프레쉬 회로(40)는 리프레쉬 동작의 실행을 지령하는 리프레시 지령 신호 /REFE를 출력한다. 리프레쉬 회로(40)는 리프레쉬 지령 신호 /REFE를 활성화시키는 지령 신호 활성화 회로(50)와 활성화된 리프레쉬 지령 신호 /REFE를 출력할지 여부를 판정하는 판정 회로(60)를 포함한다. 판정 회로(60)는 반도체 기억 장치가 대기(standby) 상태일 때에 리프레쉬 지령 신호 /REFE를 출력한다고 판정한다. 이 때문에, 이 반도체 기억 장치는 안정한 리프레쉬 동작이 가능하다.
Bibliography:Application Number: KR20020004048