METHOD FOR CONTROLLING THE QUALITY OF A LITHOGRAPHIC STRUCTURING STEP

PURPOSE: A method for controlling the quality of a lithographic structuring step is provided to reduce cost regarding an exposure process of a semiconductor wafer by decreasing the quantity of re-work. CONSTITUTION: After exposure of the semiconductor wafer, quality parameters like critical dimensio...

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Bibliographic Details
Main Authors SCHEDEL THORSTEN, ZIMMERMANN JENS, SCHMIDT SEBASTIAN
Format Patent
LanguageEnglish
Korean
Published 31.12.2002
Edition7
Subjects
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Summary:PURPOSE: A method for controlling the quality of a lithographic structuring step is provided to reduce cost regarding an exposure process of a semiconductor wafer by decreasing the quantity of re-work. CONSTITUTION: After exposure of the semiconductor wafer, quality parameters like critical dimension, overlay accuracy, alignment parameters, etc. are measured in successive inspections and compared with tolerance ranges specified dynamically by calculating the range from measured values of on or more of the other quality parameters. The tolerance ranges for overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. The tolerance ranges can also be adjusted with quality parameter measurements from the first layer to the quality parameter tolerance range of the second layer. 반도체웨이퍼(1)의 노광후, 선폭, 오버레이정확성, 정렬파라미터 등과 같은 품질파라미터(3)가 연속적인 검사로 측정되고 1이상의 다른 품질파라미터(2)의 측정값으로부터 범위를 계산하여 동적으로 특정화된 공차범위폭(9)과 비교된다. 예를 들어, 집적회로의 기능성에 영향을 미치지 않는 동일한 구조물의 더 작게 측정된 선폭에 대하여 오버레이정확성의 공차범위폭(9)을 증가시킬 수 있다. 또한, 포워드메카니즘을 사용하여, 제1층에서 품질파라미터(2)를 측정하여 제2층의 품질파라미터(3) 공차범위폭(9)으로 공차범위가 조정될 수 있다.
Bibliography:Application Number: KR20020033955