DIGITAL TELEVISION VIDEO DECODING SYSTEM WITH HARDWARE MEMORY REDUCED BY HALF AND DIGITAL TELEVISION VIDEO DECODING METHOD

• Main Authors: LEE, WON BAEK, AHN, SANG JUN, LEE, DONG HO
• Format: Patent
• Language: English; Korean
• Published: 05.12.2002
• Edition: 7
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

PURPOSE: A digital television video decoding system with a hardware memory reduced by half and a digital television decoding method are provided to prevent picture quality from being deteriorated while decreasing a memory capacity by half. CONSTITUTION: A digital television video decoding system includes a variable length decoder(21), an inverse quantization unit(22) for receiving a coefficient from the variable length decoder to output an inversely quantized coefficient, and an IDCT unit(23) for accepting the inversely quantized coefficient to output a video signal in 8x8. The system further includes an adder(24) for adding the video signal to a motion-compensated video signal, the first frame memory(25) for converting the video signal output from the adder into frames and storing the frames, and a slice buffer(26) for outputting the video signal output from the first frame memory by lines. The system also has a decimator(27) for decimating the video signal output from the adder by half, the second frame memory(28) for converting the video signal output from the decimator into frames and storing the frames, an interpolator(29) for interpolating the video signal output from the second frame memory, and a motion compensation unit(20) for compensating the video signal output from the interpolator according to a motion vector output from the variable length decoder and sending the compensated video signal to the adder.