ANALOG DIGIT PARALLEL MULTIPLIER FOR MODULO MERGEN NUMBER AND METHOD FOR APPLYING THE SAME TECHNOLOGY

• Main Authors: LEE, HUN GYU, HA, SEOK GI
• Format: Patent
• Language: English; Korean
• Published: 05.09.2002
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE: An analog digit parallel multiplier for a modulo mergen number and a method for applying the same technology are provided to give the excellent time complexity as well as to keep the area complexity. CONSTITUTION: A wiring method of the n¬2 partial products generation part is changed to the wiring method of the typical binary multiplier of the n¬2 partial products generation part. The n¬2 partial products generation part of the binary multiplier is represented by the first step signal matrix of 2nXn. The 'r' step signal matrix of the modulo parallel multiplier becomes the signal matrix of 2nXmr. The 'r+1' step signal matrix is obtained by moving the carry of the signals only to the upper bit. The signal process is simplified by considering the element region of zero value. The 'k+1' step signal matrix of 2nXn is output by repeating the method for obtaining the 'r+1' step signal matrix. The multiplying result of 2n bit is output by transmitting the signals obtained from the 'k+1' step signal matrix to a binary CLA(Carry Look Ahead) generator(11).