METAL INDUCED SELF-ALIGNED CRYSTALLIZATION OF Si LAYER FOR TFT

• Main Authors: ANDRY PAUL S, TSUJIMURA TAKATOSHI, LIBSCH FRANK R
• Format: Patent
• Language: English; Korean
• Published: 24.07.2002
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; SEMICONDUCTOR DEVICES; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

PURPOSE: Metal induced self-aligned crystallization of a silicon layer for a thin film transistor(TFT) is provided to remarkably reduce fabrication cost by improving an improved switching characteristic caused by uniform generation of a polysilicon layer and a contact layer that are formed by metal induced lateral crystallization and by performing a simplified process except a doping process. CONSTITUTION: An insulation layer(3) is deposited on a substrate(1). A source electrode(4) and a drain electrode(5) are formed from a metal-dopant compound. The metal-dopant compound is deposited on the insulation layer. A polycrystalline silicon layer is deposited on the insulation layer, the source electrode and the drain electrode. An ohmic contact layer is formed between the metal-dopant compound and the polysilicon layer(6) through migration of the dopant from the metal-dopant compound. A gate insulation layer(9) is deposited on the polysilicon layer. A gate electrode(10) is formed on the gate insulation layer. The polysilicon layer is crystallized by metal induced lateral crystallization. 본 발명은 반도체 디바이스, 박막 트랜지스터(TFT), 및 TFT를 형성하는 처리 방법을 설명한다. 본 발명에 따른 반도체 디바이스는 상단-게이트형 박막 트랜지스터(TFT)를 포함하고, 상기 상단-게이트형 TFT는 기판에 형성되고, 또한 이는: 상기 기판상에 피착된 절연층; 상기 절연층상에 피착된 금속-도펀트 (dopant) 화합물로부터 형성된 소스 전극 및 드레인 전극; 상기 절연층과 상기 소스 전극 및 상기 드레인 전극상에 피착된 폴리 실리콘 (poly-Si)층; 상기 금속-도펀트 화합물로부터의 상기 도펀트의 이동을 통해 상기 금속-도펀트 화합물과 상기 poly-Si층 사이에 형성된 저항성 접촉층; 상기 poly-Si층상에 피착된 게이트 절연층; 및 상기 게이트 절연층상에 형성된 게이트 전극을 포함하고, 상기 poly-Si층은 금속 유도 측면방향 결정화에 의해 결정화된다.