REMOVAL METHOD FOR PLANARIZING THE SEMICONDUCTOR WAFER

• Main Authors: YAMAGUCHI UI, YASUI KAN, KAWAMURA YOSHIO, NAGASAWA MASAYUKI, KATAGIRI SOUICHI
• Format: Patent
• Language: English; Korean
• Published: 04.02.2002
• Edition: 7
• Subjects: ADHESIVES; BASIC ELECTRIC ELEMENTS; CHEMISTRY; DRESSING OR CONDITIONING OF ABRADING SURFACES; DYES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS; GRINDING; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE; METALLURGY; MISCELLANEOUS APPLICATIONS OF MATERIALS; MISCELLANEOUS COMPOSITIONS; NATURAL RESINS; PAINTS; PERFORMING OPERATIONS; POLISHES; POLISHING; SEMICONDUCTOR DEVICES; TRANSPORTING

PURPOSE: To planarize a wafer surface pattern in a semiconductor device manufacturing process excellent in planarizing and superior in polish quantity uniformity and controllability. CONSTITUTION: A semiconductor wafer having at least two kinds of different films exposed thereon is planarized by polishing, using a grindstone and a process solution containing a dispersant. Adding the dispersant in the process using the grindstone improves the polishing selectivity with respect to the kind of films to obtain excellent planarizing and a good process quantity uniformity as well as the stability of process and the controllability. This improves the polishing rate, increases the throughput and makes possible reduction of the manufacturing time and cost. Especially the planarizing and the uniformity in a tradeoff relation in the prior art can be made compatible enough to facilitate the high-accuracy planarizing processes such as shallow trench element isolating process and reduce the cost. 반도체장치의 제조공정에 있어서, 평탄화성능이 높고, 또 연마량 균일성과 제어성에서 우수한 웨이퍼 표면패턴의 평탄화 가공을 행한다. 적어도 2종의 다른 박막이 노출되는 반도체웨이퍼를, 지석과, 분산제를 첨가한 가공액을 이용하여 연마에 의해 평탄화한다. 지석을 이용한 가공에 있어서, 분산제를 첨가함으로써, 막종류에 따른 연마선택비가 향상되고, 높은 평탄화성능과, 양호한 가공량 균일성을 얻을 수 있다. 또, 가공의 안정성, 제어성이 향상된다. 연마속도가 향상되고 처리량이 증가하기 때문에, 제조시간과 코스트를 저감할 수 있다. 특히, 종래 이율배반성의 관게에 있던 평탄화성능과 균일성을 양립할 수 있기 때문에, 천구(淺構)소자 분리공정 등의 고정밀도의 평탄화공정을 간이화하여, 코스트를 저감할 수 있다.