Method of manufacturing a capacitor in a semiconductor device

• Main Author: YOO, YONG SIK
• Format: Patent
• Language: English; Korean
• Published: 04.01.2002
• Edition: 7
• Subjects: ELECTRICITY

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to increase reliability and to form a capacitor having high capacitance even in a device of 0.1 micrometer, by making a diffusion barrier layer no exposed even when misalignment happens, so that a high-temperature annealing process is enabled. CONSTITUTION: The first oxide layer(12) and a nitride layer(13) are formed on a semiconductor substrate(11) having a predetermined structure. A predetermined region of the nitride layer and the first oxide layer is etched to form a contact hole exposing a predetermined region of the semiconductor substrate. A polysilicon layer(14), an ohmic contact layer and a diffusion barrier layer(16) are sequentially formed not to bury the contact hole completely. A seed layer(17) and an aluminum oxide layer are formed on the resultant structure, and the aluminum oxide layer is blank-etched to form a spacer on the sidewall of the contact hole. A glue layer and the second oxide layer are sequentially formed on the resultant structure. A predetermined region of the second oxide layer and the glue layer is etched to form a dummy oxide layer pattern. After the aluminum oxide layer spacer is eliminated, a platinum layer(21) is formed on the dummy oxide layer pattern to form a storage electrode. The second oxide layer, the glue layer and the exposed seed layer are removed. After a high dielectric layer(22) is formed on the resultant structure, an upper electrode(23) is formed. 본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 플러그가 형성된 콘택홀 측벽에 알루미늄 산화막으로 스페이서를 형성하여 저장 전극을 형성하기 위한 더미 산화막 패턴 공정에서 플러그의 확산 방지막이 노출되지 않도록 함으로써 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법이 제시된다.