Semiconductor memory device removing floating body effect and method of fabricating the same

• Main Authors: KIM, CHANG HYEON, KIM, GYEONG HO, YANG, WON SEOK
• Format: Patent
• Language: English; Korean
• Published: 22.12.2001
• Edition: 7
• Subjects: BEER; BIOCHEMISTRY; CHEMISTRY; ELECTRICITY; ENZYMOLOGY; METALLURGY; MICROBIOLOGY; MUTATION OR GENETIC ENGINEERING; SPIRITS; VINEGAR; WINE

외부에서 유입되는 잡음에 대하여 면역성이 강화된 플로팅 바디효과를 제거한 반도체 메모리소자 및 그 제조방법이 개시된다. 본 발명의 메모리소자는 반도체기판, 상기 반도체기판의 상부표면과 인접되도록 매몰되며 평행하게 배열된 복수개의 비트라인, 상기 반도체기판상에 상기 비트라인들과 절연되며 교차하도록 형성된 복수개의 워드라인 및 상기 비트라인 및 워드라인이 교차하는 단위 메모리 셀영역에 형성되어 있으며, 상기 워드라인의 측벽 일부를 따라 게이트절연막을 개재하면서 상기 비트라인상에 수직으로 제1 소오스/드레인영역, 채널영역 및 제2 소오스/드레인영역을 포함하는 복수개의 수직형 억세스 트랜지스터를 구비하며, 상기 각 억세스 트랜지스터의 채널영역을 포함하는 각 바디영역이 일체화되도록 서로 연결된다. A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged in parallel with one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a vertical channel region and a second source/drain region which are formed sequentially on the bit line. The vertical access transistor contacts a gate insulation layer formed on a portion of one side of the sidewalls of the word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated region.