MUTUAL CONNECTION LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE LAYER

• Main Authors: DONALD THOMAS QUINER, DENNIS OKUMU OUMA, SAXENA VIVEK, MISRA SUDHANSHU, JOHN MITCHELL SHARP
• Format: Patent
• Language: English; Korean
• Published: 10.09.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS

PURPOSE: To perform planarization easily during manufacture of a semiconductor device and minimize a parasitic capacitance with an adjacent wiring structure. CONSTITUTION: This is a method for forming a layout for a wiring layer of a semiconductor device to perform uniform planarization easily during manufacture of the semiconductor device. The method includes a step of determining an active wiring structure density of each of a plurality of layout regions in a wiring layout. The method further includes a step of adding a dummy filling structure to each layout region to obtain desired densities of the active wiring structure and the dummy filling structure so that uniform planarization during manufacture of the semiconductor device can be performed easily. Since the dummy filling structure is added to obtain desired densities of the active wiring structure and the dummy filling structure, the dummy filling structure is not added unnecessarily and each layout region has a uniform density.