ULTRA-SHALLOW JUNCTION DOPANT LAYER HAVING PEAK CONCENTRATION WITHIN DIELECTRIC LAYER AND PROCESS OF MANUFACTURE

PURPOSE: A ultra-shallow junction dopant layer having a peak concentration within a dielectric layer and process of manufacture is provided to embrace the technique of out diffusion from an implanted dielectric film. CONSTITUTION: The transistor includes gate(43), gate oxide(41), channel region(57),...

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Bibliographic Details
Main Authors DOKUMACI OMER H, AKATSU HIROYUKI, RENGARAJAN RAJESH, HEGDE SURYANARAYAN G, LI YUJUN, RONSHEIM PAUL A
Format Patent
LanguageEnglish
Korean
Published 07.07.2001
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A ultra-shallow junction dopant layer having a peak concentration within a dielectric layer and process of manufacture is provided to embrace the technique of out diffusion from an implanted dielectric film. CONSTITUTION: The transistor includes gate(43), gate oxide(41), channel region(57), and source/drain regions(53A, 53B) formed within substrate(40). The process of the present invention may be used to form source-drain extension regions(55) which are included between channel region(57) and source/drain regions(53A, 53B). Several spacers(47) are provided. It should be understood that source-drain extension regions(55) are formed sequentially before the addition of spacers(47). Therefore, oxide or other dielectric film(45) which forms a sidewall dielectric along gate(43) and includes a lateral component which extends along the surface(50) may constitute the dielectric film through which the source-drain extension regions(55) may be formed.
Bibliography:Application Number: KR20000072871