LOW PROFILE INTEGRATED CIRCUIT PACKAGES

PURPOSE: A method of fabricating IC package is provided to lower the height of an IC package. CONSTITUTION: The method includes the step of thinning the IC device of a chip form. At the final stage of assembly in which a chip is flip chip-bonded to a substrate, and the backside of the chip is expose...

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Bibliographic Details
Main Authors TAI KING L, DUDDERAR THOMAS D, DEGANI YINON
Format Patent
LanguageEnglish
Korean
Published 06.07.2001
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A method of fabricating IC package is provided to lower the height of an IC package. CONSTITUTION: The method includes the step of thinning the IC device of a chip form. At the final stage of assembly in which a chip is flip chip-bonded to a substrate, and the backside of the chip is exposed due to thinning. When the method is used, the chip of which final thickness is about 2 to 8 mils can be manufactured and the whole thickness of the package is considerably reduced. 본 발명은 박막화 기법을 이용하여 IC 패키지용 박형 타일을 제조하는 방법을 제공한다. 본 방법은 칩 형태의 IC 디바이스를 박막화하는 단계를 포함한다. 이것은 칩이 기판에 대해 플립-칩 접합되고 칩의 후면이 박막화중에 노출되는 조립의 최종 단계에서 수행된다. 본 방법을 이용하면, 2∼8밀리 정도의 최종 칩 두께가 얻어질 수 있으며, 총 패키지 두께는 매우 감소된다.
Bibliography:Application Number: KR20000061794