SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• Main Authors: YAHATA HIDEHARU, KOKUBO MASARU, MIYASHITA HIROKI, NAKAGOME YOSHINOBU, OKUDA YUICHI
• Format: Patent
• Language: English; Korean
• Published: 15.05.2001
• Edition: 7
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE: To realize high accuracy and low power consumption by slectrically isolating an element formation region for forming a clock generating circuit and an element formation region for constituting a digital circuit, which is formed on a semiconductor substrate. CONSTITUTION: Sence amplifier 2 are formed in respective memory cell arrays 1 of a memory chip where these amplifiers 2 are provided such that they are made to exist in the interior of respective triple wells forming the memory cell arrays 1. A DLL (clock generating circuit) analog part 3 is provided in the interior of a triple well in the central part of the memory chip, a triple well in the analog part 3 is provided so that it is made to be isolated from the triple wells including the arrays and the amplifiers 2 to make them adjacent to the part 3, and DLL digital parts 4 are made to exist on the outside of the triple wells. As a result, a low power consumption in a semiconductor integrated circuit device can be achieved with high accuracy. 외부단자에서 입력된 입력클록신호를 가변지연회로에서 지연한 지연신호에 의거한 신호와, 상기 입력클록신호를 위상비교회로에서 위상비교하고, 양자가 일치하도록 제어회로에서 상기 가변지연회로의 지연시간을 제어하여 내부클록신호를 형성하는 클록발생회로에 있어서, 상기 클록발생회로와 그것에 의해 형성된 클록신호에 의해 동작하는 내부회로를 공통의 반도체 기판상에 형성하고, 상기 클록발생회로가 형성되는 소자형성영역과, 상기 반도체기판상에 형성되는 상기 디지털회로를 구성하는 소자형성영역을 소자분리기술에 의해 전기적으로 분리한다. 전원경로도 다른 디지털회로와 독립시킨다.