DEVICE AND METHOD FOR CONTROLLING PLL

PURPOSE: A device and a method for controlling PLL(Phase Locked Loop) are provided to shorten the lock up time of a phase detector by boosting a frequency generated in the PLL to a desired control voltage. CONSTITUTION: The control device of PLL comprises a memory(110), a signal converter(10) and a...

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Bibliographic Details
Main Author BAE, YUN SIK
Format Patent
LanguageEnglish
Korean
Published 05.03.2001
Edition7
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Summary:PURPOSE: A device and a method for controlling PLL(Phase Locked Loop) are provided to shorten the lock up time of a phase detector by boosting a frequency generated in the PLL to a desired control voltage. CONSTITUTION: The control device of PLL comprises a memory(110), a signal converter(10) and a controller(100). Reference data proportional to the frequency to be generated in a PLL in accordance with the selection of a channel or a band are stored in the memory(110). The signal converter(10) varies the voltage of a signal output from a phase detector(140) in accordance with a predetermined control signal. The controller(100) generates the predetermined control signal on the basis of the reference data stored in the memory.
Bibliography:Application Number: KR19990033194