A LAYOUT AND METHOD FOR FLASH MEMORY WITH NO SAS PROCESS

• Main Authors: MEHRAD FREIDOON, XIA JIE, AMBROSE THOMAS M
• Format: Patent
• Language: English; Korean
• Published: 26.02.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE: A flash memory is provided to remove necessity for a self-matching process, without increasing cost by providing an intermediate conductor on a floating gate, a hard mask insulating layer on a control gate, a memory cell containing a source region adjacent to the floating gate, and a drain region arranged on the opposite side of the source region and a source contact. CONSTITUTION: When a hard mask layer(100) is silicon nitride, a conductive layer(91) is formed so that it is overlapped with a part of a gate stack. The overlap is formed by extending the width of an opening before the deposition of the conductive layer(91). An overlapping region(140) is typically narrower than the width of a gate stack(145). The overlap can be used for increasing positioning error tolerance in photolithographic processing used for reducing the resistance of a source contact line or forming a source contact opening. The source regions of the separated memory cells are brought into contact with one another by the conductive layer(91) which forms continuous conductive paths. SAS 공정을 포함하지 않는 FLASH 메모리용의 레이아웃 및 방법이 설명된다. 레이아웃은 일련의 메모리셀(10)의 소스 영역들을 접속시켜 소스 라인(24)을 형성하는 소스 콘택트(91)를 포함한다. 소스 콘택트는 소스 콘택트(91) 형성동안 제어 게이트(18)를 절연시키는 메모리셀 게이트 스택(110, 115)의 일부로서 하드 마스크 절연체층(100)을 이용하여 형성된다.