METHOD AND DEVICE FOR INCREASING A WRITING EFFICIENCY IN COMPUTER PROCESSOR

• Main Authors: LEE, HUN JU, KIM, JIN GI
• Format: Patent
• Language: English
• Published: 16.10.2000
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE: A method and device for increasing a writing efficiency in a computer processor is provided to improve the writing efficiency of the computer processor in a memory by preventing the computer processor from being occupied during the access time when writing data in the various memories. CONSTITUTION: A device for increasing a writing efficiency(30') is connected between a computer processor(10) and a memory device(20). The device for increasing a writing efficiency(30') in the computer processor(10) has a map decode arbiter unit(31'), a latch buffer and data arbiter unit(32') and an early acknowledge and control unit(33'). The map decode arbiter unit(31') receives an address signal from the computer processor(10). If the signal received from the computer processor(10) is an address signal corresponding to the accessed memory device(20), the map decode arbiter unit(31') outputs a chip selecting signal to the memory device(20) after being written. If not, the map decode arbiter unit(31') outputs a chip selecting signal to the memory device(20) immediately. The latch buffer and data arbiter unit(32') receives a data signal from the computer processor(10) and outputs a data signal selectively. A registered IC(integrated circuit) or PLD(programmable logic device) is used for the latch buffer unit. The early acknowledge and control unit(33') receives a latched signal from the latch buffer and data arbiter unit(32') and outputs a pass closing signal to the latch buffer and data arbiter unit(32').