INTEGRATED CIRCUIT WITH DIFFERING GATE OXIDE THICKNESS AND PROCESS FOR MAKING SAME

PURPOSE: A semiconductor process for manufacturing a semiconductor substrate is provided, particularly for an MOS integrated circuit in which some transistors are processed to have thinner gate oxide than others. CONSTITUTION: A semiconductor process for a semiconductor substrate is provided. The su...

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Main Authors GARDNER MAKR I, HAUSE FRED N
Format Patent
LanguageEnglish
Published 25.05.2000
Edition7
Subjects
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Abstract PURPOSE: A semiconductor process for manufacturing a semiconductor substrate is provided, particularly for an MOS integrated circuit in which some transistors are processed to have thinner gate oxide than others. CONSTITUTION: A semiconductor process for a semiconductor substrate is provided. The substrate comprises a first region having p-type silicon and a second region having n-type silicon. The second region is positioned side wise to the first region. On an upper side of the substrate is provided an oxide layer. A silicon nitride layer is introduced to the oxide layer. The silicon nitride layer over the first region is removed and nitrogen impurities are introduced. And a gate dielectric layer is formed on the first and second region.
AbstractList PURPOSE: A semiconductor process for manufacturing a semiconductor substrate is provided, particularly for an MOS integrated circuit in which some transistors are processed to have thinner gate oxide than others. CONSTITUTION: A semiconductor process for a semiconductor substrate is provided. The substrate comprises a first region having p-type silicon and a second region having n-type silicon. The second region is positioned side wise to the first region. On an upper side of the substrate is provided an oxide layer. A silicon nitride layer is introduced to the oxide layer. The silicon nitride layer over the first region is removed and nitrogen impurities are introduced. And a gate dielectric layer is formed on the first and second region.
Author GARDNER MAKR I
HAUSE FRED N
Author_xml – fullname: GARDNER MAKR I
– fullname: HAUSE FRED N
BookMark eNqNiksKwjAURTPQgb89PHAsRLOCkLwkj9BWkojOSpE4krRQ948NuADv5Fw4Z8tWZSx5wwK1CW2QCTUoCupGCe6UHGgyBhdrwS4SugdphORI-RZjBNlquIZO1W-6AI30tY2ywT1bv4b3nA8_7tjRYFLulKexz_M0PHPJn96HC68TnJ-FFP9VX6o4McU
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Edition 7
ExternalDocumentID KR20000030013A
GroupedDBID EVB
ID FETCH-epo_espacenet_KR20000030013A3
IEDL.DBID EVB
IngestDate Fri Jul 19 13:56:35 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_KR20000030013A3
Notes Application Number: KR19997001315
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000525&DB=EPODOC&CC=KR&NR=20000030013A
ParticipantIDs epo_espacenet_KR20000030013A
PublicationCentury 2000
PublicationDate 20000525
PublicationDateYYYYMMDD 2000-05-25
PublicationDate_xml – month: 05
  year: 2000
  text: 20000525
  day: 25
PublicationDecade 2000
PublicationYear 2000
RelatedCompanies ADVANCED MICRO DEVICES INC
RelatedCompanies_xml – name: ADVANCED MICRO DEVICES INC
Score 2.518989
Snippet PURPOSE: A semiconductor process for manufacturing a semiconductor substrate is provided, particularly for an MOS integrated circuit in which some transistors...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title INTEGRATED CIRCUIT WITH DIFFERING GATE OXIDE THICKNESS AND PROCESS FOR MAKING SAME
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000525&DB=EPODOC&locale=&CC=KR&NR=20000030013A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8gGvVNUeMHmiaavS2yT-CBmNFubC5jpA7lzWyjJCZmEJnx3_c6QHni7dJrLm3T39314-4AHrp2LoxOJ1NnemuqmmmOmMs6XVUTaautZ-1ct2SgcDS0_bH5PLEmNfjcxMJUeUJ_quSIiKgc8V5W-nrxf4nFqr-Vy8fsA5vmT17SY8rmdCxvOS2F9XvuKGYxVSjthVwZ8hUPNzR6PM4e7KMj3ZZ4cF_7Mi5lsW1UvBM4GKG8ojyFmigacEQ3tdcacBitn7yRXKNveQZc5q8dcAeVDaEBp-MgIW9B4hMWeF6VG4oMkEniScBckvgBDWVJDeIMGRnxmEoaD30kckLZ98WJ3HO499yE-ioO7v1vLd5Dvj0T4wLqxbwQl0Dkg6awtaku8tScpkbamlmm0NLM6NqprhlX0Nwl6Xo3-waOVzHolqpbTaiXX9_iFq1xmd1Vi_gL5E2Ftg
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8gGvFNUYOK2kSzt0X2CTwQM7qN1bGNzKG8kW6UxMQMIjP--7YDlCfeLr3m0jb93V0_7g7gsWtmTOt0UnmutmayTjOOubTTlRVGW201bWeqIQKFg9D0xvrLxJhU4HMbC1PmCf0pkyNyRGUc70Wpr5f_l1h2-bdy9ZR-8KbFs5v0bGl7Oha3nIZk93vOKLIjLGHc82MpjNc8vqG5x2MdwCF3stsCD85bX8SlLHeNinsKRyMuLy_OoMLyOtTwtvZaHY6DzZM3JzfoW51DLPLXDmKLKxuESYzHJEHvJPGQTVy3zA2FBpyJogmxHZR4BPuipAayQhuN4ggLmh_6UGD5ou-rFTgX8OA6CfZkPrjp31pM_Xh3JtolVPNFzhqAxIMmM5WZyjKqz6hGW3NDZwpNta5JVUW7guY-Sdf72fdQ85JgOB2S0L-Bk3U8uiGrRhOqxdc3u-WWuUjvygX9BVZRiKk
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=INTEGRATED+CIRCUIT+WITH+DIFFERING+GATE+OXIDE+THICKNESS+AND+PROCESS+FOR+MAKING+SAME&rft.inventor=GARDNER+MAKR+I&rft.inventor=HAUSE+FRED+N&rft.date=2000-05-25&rft.externalDBID=A&rft.externalDocID=KR20000030013A