A MODEL FOR AN APPARATUS OF CLUSTERED PHOTOLITHOGRAPHY FOR ACHIEVING FABWAFER FABRICATION FACILITIES-LEVEL SIMULATION AND A METHOD FOR SIMULATING USING IT

• Main Authors: ROBERT MORRISON JAMES, PARK, KYUNG SU, PARK, JUNG YEON, BAE, SANG YOON
• Format: Patent
• Language: English; Korean
• Published: 14.06.2018
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CINEMATOGRAPHY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

An object of the present invention is to provide a simulation apparatus of a wafer fabrication process level including a photolithography cluster apparatus capable of providing accurate prediction and optimized fabrication process and time reduction, and a simulation method using the same. The simulation apparatus according to an embodiment of the present invention comprises: an apparatus model determination unit for determining an apparatus model for a photolithography cluster apparatus simulation; a parameter calculation unit for calculating a parameter corresponding to the determined model; and a process simulation unit for driving the simulated photolithography cluster apparatus using the calculated parameters. The present invention provides photolithography cluster apparatus simulation of a wafer fabrication process (FAB) level. 본 발명의 실시 예에 따른 시뮬레이션 장치는, 포토리소그래피 클러스터 장치 시뮬레이션을 위한 장치 모델을 결정하는 장치 모델 결정부; 상기 결정된 모델에 대응되는 파라미터를 산출하는 파라미터 산출부; 및 상기 산출된 파라미터를 이용하여, 시뮬레이션된 포토리소그래피 클러스터 장치를 구동하는 공정 시뮬레이션부를 포함하여, 웨이퍼 제조 공정(FAB) 레벨의 포토리소그래피 클러스터 장치 시뮬레이션을 제공한다.