SEMI-CONDUCTOR STACKING PACKAGE VIA INTERWIRING

PURPOSE: A semiconductor stack package using inter-wiring is provided to reduce the volume of the semiconductor stack package by filling an inner empty space with molding resins and surrounding the outer surface of a laminate with the molding resins. CONSTITUTION: A plurality of unit devices(100) co...

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Bibliographic Details
Main Author CHAE, JANG SOO
Format Patent
LanguageEnglish
Korean
Published 08.10.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A semiconductor stack package using inter-wiring is provided to reduce the volume of the semiconductor stack package by filling an inner empty space with molding resins and surrounding the outer surface of a laminate with the molding resins. CONSTITUTION: A plurality of unit devices(100) composed of a semiconductor chip and a flexible substrate are vertically laminated on a semiconductor stack package(P). The semiconductor chip is mounted on the flexible substrate. A conductive pattern is formed on a mounting surface of the semiconductor chip. The end of the conductive pattern is formed in the side of the flexible substrate. A connection member electrically connects the end of the conductive pattern. Each unit device is electrically connected with each other.
Bibliography:Application Number: KR20110051775