CURRENT MODE LOGIC DUAL EDGE TRIGGERED SAMMPLING CIRCUIT AND FLIP-FLOP CIRCUIT

• Main Authors: YANG, KYOUNG HOON, CHUNG, KYU HYUN
• Format: Patent
• Language: English; Korean
• Published: 18.11.2011
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

PURPOSE: A CML dual edge trigger sampling circuit and a flip-flop circuit are provided to reduce noise which is generated in an operation process by forming a top and bottom and right and left symmetry structure. CONSTITUTION: A CML(Current Mode Logic) dual edge trigger sampling circuit comprises a current source(310), an input-output part(320), a current sink(340), an output node(370), a transistor part, and a loader(360). The current source outputs a current. The input-output part creates an output signal according to an input signal. A first transistor(350) sanctions a constant current to the output node regardless of the change of the output signal by controlling opening and shutting of the current which is created from the current source. The loader sanctions the current of the output node to the current sink. The output node creates an output signal between the first transistor and the loader. The first transistor comprises a first transistor(352) which is inputted a first input signal and a second transistor(354) which is inputted a second input signal.