STACKED SEMICONDUCTOR PACKAGE

A stacked semiconductor package is provided to reduce thickness and dimension of a stacked semiconductor package by connecting a wire extended from a bonding pad of a bottom semiconductor chip to a bonding pad of a top semiconductor chip. A first semiconductor chip(20) is arranged on a first surface...

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Bibliographic Details
Main Author CHUNG, QWAN HO
Format Patent
LanguageEnglish
Published 02.02.2009
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A stacked semiconductor package is provided to reduce thickness and dimension of a stacked semiconductor package by connecting a wire extended from a bonding pad of a bottom semiconductor chip to a bonding pad of a top semiconductor chip. A first semiconductor chip(20) is arranged on a first surface(1) of a substrate(10), is separated from a bonding pad(4), and includes a first semiconductor chip body(24), a first bonding pad(26), a rewiring(28), and a chip selection rewiring. The first semiconductor chip body a top surface(21) and a bottom surface(22). The bottom surface of the first semiconductor chip body is faced with the first surface of the substrate, and is attached on the first surface of the substrate by a first adhesive member(27). The first bonding pad is arranged on the top surface of the first semiconductor chip body. A plurality of first bonding pads is arranged according to an edge of one side of the top surface of the first semiconductor chop body. The rewiring is arranged on the top surface of the first semiconductor chip body, and corresponds to each first bonding pad. A second semiconductor chip includes a second semiconductor chip body and a second bonding pad.
Bibliography:Application Number: KR20070088386