TAPE CIRCUIT SUBSTRATE HAVING CONNECTED TEST WIRING AND METHOD FOR EXAMINING THEREOF
A tape circuit substrate having a test wiring and a method for examining the same are provided to reduce an occupied area of IC patterns by reducing the number of test pads. A base film(10) includes a chip mounting part on which a semiconductor chip is mounted. The base film is formed with an insula...
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| Main Authors | , , , |
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| Format | Patent |
| Language | English |
| Published |
14.12.2007
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A tape circuit substrate having a test wiring and a method for examining the same are provided to reduce an occupied area of IC patterns by reducing the number of test pads. A base film(10) includes a chip mounting part on which a semiconductor chip is mounted. The base film is formed with an insulating material. A plurality of bypass wirings(20) are formed on the base film in order to bypass the chip mounting part. A plurality of test wirings(30) are formed on the base film in order to be connected to the bypass wirings. The first test wiring and the second test wiring of the test wirings are connected to each other. The third test wiring is formed between the first test wiring and the second test wiring on the base film. |
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| AbstractList | A tape circuit substrate having a test wiring and a method for examining the same are provided to reduce an occupied area of IC patterns by reducing the number of test pads. A base film(10) includes a chip mounting part on which a semiconductor chip is mounted. The base film is formed with an insulating material. A plurality of bypass wirings(20) are formed on the base film in order to bypass the chip mounting part. A plurality of test wirings(30) are formed on the base film in order to be connected to the bypass wirings. The first test wiring and the second test wiring of the test wirings are connected to each other. The third test wiring is formed between the first test wiring and the second test wiring on the base film. |
| Author | LEE, SUNG SOO JEON, JE SEOG YOON, SUK BUM CHUNG, CHAN SIK |
| Author_xml | – fullname: YOON, SUK BUM – fullname: JEON, JE SEOG – fullname: LEE, SUNG SOO – fullname: CHUNG, CHAN SIK |
| BookMark | eNqNiksKwjAUALPQhb87PHAttEipLtPkxQRpUpJXdVeKxJWkhXp_pOABXA3MzJot0pDiihHxBkEYL1pDENoqkOeEoPnN2AsIZy0KQgmEgeBu_Gy5lVAjaSdBOQ_44LWxcyCNHp3asuWrf09x9-OG7RWS0Ic4Dl2cxv4ZU_x0V59nWXkqzmVRVfnxv-sLMgky8w |
| ContentType | Patent |
| DBID | EVB |
| DatabaseName | esp@cenet |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Medicine Chemistry Sciences |
| ExternalDocumentID | KR100785975BB1 |
| GroupedDBID | EVB |
| ID | FETCH-epo_espacenet_KR100785975BB13 |
| IEDL.DBID | EVB |
| IngestDate | Fri Jul 19 15:54:50 EDT 2024 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-epo_espacenet_KR100785975BB13 |
| Notes | Application Number: KR20060133182 |
| OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071214&DB=EPODOC&CC=KR&NR=100785975B1 |
| ParticipantIDs | epo_espacenet_KR100785975BB1 |
| PublicationCentury | 2000 |
| PublicationDate | 20071214 |
| PublicationDateYYYYMMDD | 2007-12-14 |
| PublicationDate_xml | – month: 12 year: 2007 text: 20071214 day: 14 |
| PublicationDecade | 2000 |
| PublicationYear | 2007 |
| RelatedCompanies | STECO, LTD |
| RelatedCompanies_xml | – name: STECO, LTD |
| Score | 2.6954541 |
| Snippet | A tape circuit substrate having a test wiring and a method for examining the same are provided to reduce an occupied area of IC patterns by reducing the number... |
| SourceID | epo |
| SourceType | Open Access Repository |
| SubjectTerms | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
| Title | TAPE CIRCUIT SUBSTRATE HAVING CONNECTED TEST WIRING AND METHOD FOR EXAMINING THEREOF |
| URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071214&DB=EPODOC&locale=&CC=KR&NR=100785975B1 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwEA9jivqmU_FjSkDpW3Fdv-xDkTZNbR1LR5fNvUmzVhChG67iv-8lbM6nvYU7OJILl_vI5ReE7o2qdFxLOHph2xJUu1foBdD0CkLtd8v1XDFXaJ_MSSbWy8yetdDn5i2Mwgn9UeCIYFFzsPdGndfLbRErUr2VqwfxAaTFU8z9SNtkx67RNywtCn06yqKMaIT4g1xjuS-bAR4heLZDSJX2II52Zf8XnYbyWcryv0-Jj9H-CMTVzQlqVXUHHZLN12sddDBc33jDcG18q1PEeTCimKQ5maQcjyeh_O-YU5wE05Q9Y5IxRgkcRJjTMcevqexzwAGL8JDyJIsw5HuYzoJhyiSDJzSnWXyG7mLKSaLD9N7-lPE2yLdLCQ3zHLXrRV1dIOyU5rywBPjgUgLEOJ7oFZ4NOyFMryg98xJ1d0m62s2-Rkeqqmn0dcPqonbz9V3dgDtuxK1S4y-rV4an |
| link.rule.ids | 230,309,783,888,25578,76884 |
| linkProvider | European Patent Office |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwEA9jivNNp-LH1IDSt-K6fq0PRdo0tXVrOrps7m20awURuuEq_vteyuZ82lu4gyO5cLmPXH5B6FEpcsPUMkNOdV2AandTOQWaXECo_a6ZlpktarRPZgQT7XWmzxroc_sWpsYJ_anBEcGiFmDvVX1er3ZFLK_urVw_ZR9AWj773PakbXZsKj1FkzzXpqPYi4lEiD1IJJbYohmgD8Gz7kKqdAAxdl8A7dOpK56lrP77FP8EHY5AXFmdokZRtlGLbL9ea6OjaHPjDcON8a3PEOfOiGISJmQScjyeuOK_Y05x4ExD9oJJzBglcBBhTsccv4WizwE7zMMR5UHsYcj3MJ05UcgEgwc0obF_jh58ykkgw_Tmf8qYD5LdUlxFvUDNclkWlwgbubpItQx8cC4AYgwr66aWDjuRqVaaW-oV6uyTdL2ffY9aAY-G82HIBjfouK5wKj1Z0TqoWX19F7fgmqvsrlbpLySIiZc |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=TAPE+CIRCUIT+SUBSTRATE+HAVING+CONNECTED+TEST+WIRING+AND+METHOD+FOR+EXAMINING+THEREOF&rft.inventor=YOON%2C+SUK+BUM&rft.inventor=JEON%2C+JE+SEOG&rft.inventor=LEE%2C+SUNG+SOO&rft.inventor=CHUNG%2C+CHAN+SIK&rft.date=2007-12-14&rft.externalDBID=B1&rft.externalDocID=KR100785975BB1 |