METHOD FOR MANUFACTURING ISOLATION LAYER OF SEMICONDUCTOR DEVICE PREVENTING THINNING AT TRENCH TOP CORNER USING DOUBLE O3-TEOS LAYER

• Main Authors: PI, SEUNG HO, WON, DAE HUI
• Format: Patent
• Language: English; Korean
• Published: 06.11.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE: A method for manufacturing an isolation layer of a semiconductor device is provided to prevent thinning at a trench top corner by using a double O3-TEOS(Tetra Ethyl Ortho Silicate) oxide layer. CONSTITUTION: A pad oxide layer(12) and a nitride layer are sequentially formed on a substrate(10). A trench is formed in the substrate. A thermal oxide layer(18) is grown on the trench. Plasma treatment is performed. A first O3-TEOS oxide layer is filled in the trench and planarized by CMP(Chemical Mechanical Polishing) to expose the nitride layer. The exposed nitride layer is removed by wet-etching. A second O3-TEOS oxide layer is formed on the resultant structure and planarized, thereby forming an isolation layer(22). 본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 트랜치가 형성되는 반도체 기판 하부의 필드영역에 O-TEOS 산화막을 형성하되, 액티브영역 보다 높게 형성함으로써 트랜치 모서리 부분에서의 씨닝(thinning)현상을 방지하여 소자의 전기적 특성을 향상시키는 기술이다.