METHOD FOR FABRICATING CONTACT HOLE FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE

• Main Authors: SON, JIN SEOK, YANG, YE SEOK
• Format: Patent
• Language: English; Korean
• Published: 31.10.2002
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE: A method for fabricating a contact hole for forming a capacitor of a semiconductor device is provided to increase a design margin by the width of a sidewall spacer by forming a sidewall spacer made of polysilicon on the sidewall of a portion where the contact hole for forming the capacitor is to be formed while using a process for forming the contact hole for fabricating a bitline and a process for forming the bitline. CONSTITUTION: The first interlayer dielectric(3) is deposited on a semiconductor substrate(1) having a filed oxide layer(2) and a MOS(Metal Oxide Semiconductor) transistor. A contact hole for forming the bitline and a temporary contact hole for forming the capacitor are formed. Polysilicon for the bitline is deposited and an ion implantation process is performed. A silicide layer and a nitride layer are sequentially deposited. The first photoresist pattern for forming the bitline is formed. The nitride layer, the silicide layer and the polysilicon for the bitline are etched to form the bitline by using the first photoresist pattern as an etch barrier while the sidewall spacer made of polysilicon is formed in a capacitor formation region. Residual photoresist is removed and the second interlayer dielectric(9) is formed. The second photoresist pattern for defining the contact hole for the capacitor is formed. The second interlayer dielectric is etched to form the contact hole for forming the capacitor by using the second photoresist pattern as an etch barrier. Residual photoresist is eliminated. 1. 청구범위에 기재된 발명이 속한 기술분야 반도체 소자 제조 방법 2. 발명이 해결하려고 하는 기술적 과제 종래 방법으로는 콘택홀 형성시 식각해야할 층간절연막이 두껍기 때문에 식각후 콘택홀의 상부 크기와 하부 크기의 차이가 크기에 정확한 콘택홀을 형성할 수 없다는 문제점을 해결하고자 함. 3. 발명의 해결방법의 요지 비트 라인을 형성하기 위한 콘택홀을 형성하는 공정과 비트 라인을 제조하는 공정을 이용하여 캐패시터를 형성하기 위한 콘택홀이 형성될 부분의 측벽에 폴리실리콘으로된 측벽 스페이서를 형성하여 좀 더 용이하게 캐패시터를 형성하기 위한 콘택홀을 제조하고자 함. 4. 발명의 주요한 용도 캐패시터를 형성하기 위한 콘택홀을 형성하는데 이용됨.