SEMICONDUCTOR INTEGRATED CIRCUIT HAVING STAND-BY CURRENT REDUCING CIRCUIT

• Main Authors: KAWASE YASUSHI, AKIBA TAKESADA, TACHIBANA TOSHIKAZU, WATANABE TAKAO, KAWAHARA TAKAYUKI, KAWAJIRI YOSHIKI, AOKI MASAKAZU, HORIGUCHI MASASHI, KITSUKAWA GORO
• Format: Patent
• Language: English; Korean
• Published: 12.12.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE: A semiconductor integrated circuit is provided to reduce the current consumption in the stand-by state even when CMOS circuit is shrunken and the subthreshold current increases. CONSTITUTION: A switching P-channel MOS transistor(S1) has a source, a drain and a gate. A plurality of CMOS circuits(C1-Cn) have a first power supply node(N1) and a second power supply node(N2), wherein the source of the switching P-channel MOS transistor(S1) is coupled with a first operating potential(VC), the gate of the switching P-channel MOS transistor(S1) is controlled by a control signal(T1), the drain of the switching P-channel MOS transistor is coupled with the first power supply node(N1) of the plurality of CMOS circuits, and the second power supply node of the plurality of CMOS circuits is coupled with a second operating potential(VS). The first power supply node(N1) and the second power supply node of the plurality of CMOS circuits are short-circuited, wherein second subthreshold currents flow through source-drain paths of P-channel MOS transistors of the plurality of CMOS circuits in case that signals values of which are smaller than threshold voltages of the P-channel MOS transistors are respectively supplied between the sources and the gates of the P-channel MOS transistors.