HIGH-SPEED DRAM

• Main Author: LEE, U YEONG
• Format: Patent
• Language: English; Korean
• Published: 01.08.2001
• Edition: 7
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PURPOSE: A high-speed DRAM is provided to prevent unnecessary time required for precharging by precharging an activated block and simultaneously activating another block. CONSTITUTION: The first and second shift registers(10,11) receive and store a block address signal when a row active signal is activated. The third shift register(12) shifts and stores a previous block address signal stored in the first shift register(10) when another block address signal is input. A comparator(20) compares a current block address signal(block address2) stored in the second shift register(11) with the previous block address signal(block address1) stored in the third shift register(12). A block active delay part(30) determines whether activation of the current block is identical to precharge timing of a previous block or not, by selectively delaying activation of the current block according to an output signal of the comparator(20).