METHOD FOR FABRICATING GATE ELECTRODE USING ANTI-REFLECTIVE LAYER AND METHOD FOR FORMING SELF-ALIGNED CONTACT USING THE SAME

PURPOSE: A method for fabricating a gate electrode using an anti-reflective layer and a method for forming a self-aligned contact using the same are provided to form a gate electrode having a sufficient insulating margin between an electrode and a contact by using an anti-reflective layer. CONSTITUT...

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Main Authors SHIN, GYEONG SEOP, LEE, WON SEOK, JUNG, SANG SEOP
Format Patent
LanguageEnglish
Korean
Published 15.01.2001
Edition7
Subjects
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Abstract PURPOSE: A method for fabricating a gate electrode using an anti-reflective layer and a method for forming a self-aligned contact using the same are provided to form a gate electrode having a sufficient insulating margin between an electrode and a contact by using an anti-reflective layer. CONSTITUTION: A doped polysilicon layer and a metallic silicide layer are formed on a semiconductor substrate(10). A capping layer is formed on the metallic silicide layer. An anti-reflective layer is formed on the capping layer. A protective layer is formed on the anti-reflective layer. The protective layer, the anti-protective layer and the capping layer are etched by performing a photo-lithography process. A mask pattern(38) including a capping layer pattern(32a), an anti-respective layer pattern(34a) and a protective layer pattern(36a) is formed by etching the protective layer, the anti-protective layer, and the capping layer. A gate electrode(26) is formed by etching the metallic silicide layer and the doped polysilicon layer.
AbstractList PURPOSE: A method for fabricating a gate electrode using an anti-reflective layer and a method for forming a self-aligned contact using the same are provided to form a gate electrode having a sufficient insulating margin between an electrode and a contact by using an anti-reflective layer. CONSTITUTION: A doped polysilicon layer and a metallic silicide layer are formed on a semiconductor substrate(10). A capping layer is formed on the metallic silicide layer. An anti-reflective layer is formed on the capping layer. A protective layer is formed on the anti-reflective layer. The protective layer, the anti-protective layer and the capping layer are etched by performing a photo-lithography process. A mask pattern(38) including a capping layer pattern(32a), an anti-respective layer pattern(34a) and a protective layer pattern(36a) is formed by etching the protective layer, the anti-protective layer, and the capping layer. A gate electrode(26) is formed by etching the metallic silicide layer and the doped polysilicon layer.
Author SHIN, GYEONG SEOP
JUNG, SANG SEOP
LEE, WON SEOK
Author_xml – fullname: SHIN, GYEONG SEOP
– fullname: LEE, WON SEOK
– fullname: JUNG, SANG SEOP
BookMark eNqNjD0LwjAUADPo4Nd_eOBcaBXp_Jq-tME0gfQpOJUicZK2UEd_vBY6ODodHMetxaLru7AS74q4dDko50Fh5rVE1raAApmADEn2Lie41JNEyzrypCatrwQGb-S_Noffi_PVFNdkVIRGF5ZykM4ySp4_XBLUWNFWLB_tcwy7mRuxV8SyjMLQN2Ec2nvowqs5-ySOD-kpPSZZlhz_qz6oXz1J
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Edition 7
ExternalDocumentID KR100275731BB1
GroupedDBID EVB
ID FETCH-epo_espacenet_KR100275731BB13
IEDL.DBID EVB
IngestDate Fri Jul 19 15:46:31 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
Korean
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_KR100275731BB13
Notes Application Number: KR19980018828
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010115&DB=EPODOC&CC=KR&NR=100275731B1
ParticipantIDs epo_espacenet_KR100275731BB1
PublicationCentury 2000
PublicationDate 20010115
PublicationDateYYYYMMDD 2001-01-15
PublicationDate_xml – month: 01
  year: 2001
  text: 20010115
  day: 15
PublicationDecade 2000
PublicationYear 2001
RelatedCompanies SAMSUNG ELECTRONICS CO., LTD
RelatedCompanies_xml – name: SAMSUNG ELECTRONICS CO., LTD
Score 2.4955306
Snippet PURPOSE: A method for fabricating a gate electrode using an anti-reflective layer and a method for forming a self-aligned contact using the same are provided...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title METHOD FOR FABRICATING GATE ELECTRODE USING ANTI-REFLECTIVE LAYER AND METHOD FOR FORMING SELF-ALIGNED CONTACT USING THE SAME
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010115&DB=EPODOC&locale=&CC=KR&NR=100275731B1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NS8MwFA9jinrTqfgxJaD0VlzXZrWHIm2atnP9GFkc8zSWrgUZbMNVvPjHm9TN7bRLCC_hQQK_95Hk_QLAY2vCkTaxOupUOHdVILGlWjoSDeKZpCMz2rxi-0w64ZvxOkKjGphtamEqntDvihxRICoTeC8re73cHmJ51dvK1RP_EKLFi89sT9lkx5qMcBTPtUk_9VKsYGz3qJJQWzKNmsjUNVekSgcijjYlHMjQlWUpy12f4p-Cw75QNy_PQG22aIBjvPl6rQGO4vWNt-iuwbc6Bz8xYWHqQZG3Qd9xaVUDnAQwcBiBJCKY0dQjUH6kEUAnYV2VEl-Ku0MCI-edUCH14K6WlMZy8oBEvupE3SAhHsRpwhzM1npYSODAickFePAJw6EqljH-37Rxj26X7Gr6JajPF_P8CkDTEikMb2dFUUwNpOfcMCaZNIwWz59Ru7gGzX2abvYP34KTv1damqqhJqiXn1_5nXDbJb-vtvsXYrWQKQ
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFA5jivNNp-JlakDpW3Fdm9U-FGnT9OJ6GV0c82ksXQsy2Iar-OKPN6mb29NeQjgJBxL4ziXJ-QLAY3vCkDIxuvKUO3eZI7EtGyriDWKZoCPTOqxi-4y7_pv2OkKjGphtamEqntDvihyRIyrjeC8re73cHmI51dvK1RP74KLFi0tNR9pkx4qIcCTHNkk_cRIsYWz2UilOTcE0qiNdVWyeKh3wGFsXcCBDW5SlLHd9insCDvtc3bw8BbXZogkaePP1WhMcResbb95dg291Bn4iQv3EgTxvg65lp1UNcOxBz6IEkpBgmiYOgeIjDQ9aMQ3klLhCHAwJDK13knKpA3e1JGkkJg9I6MpWGHgxcSBOYmphutZDfQIHVkTOwYNLKPZlvozx_6aNe-l2ybaiXoD6fDHPLwHUDZ7CsE5WFMVUQ2rONG2SCcNosPwZdYor0Nqn6Xr_8D1o-DQKx2EQ927A8d-LLUVWUAvUy8-v_Ja78JLdVVv_C1PHkxw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=METHOD+FOR+FABRICATING+GATE+ELECTRODE+USING+ANTI-REFLECTIVE+LAYER+AND+METHOD+FOR+FORMING+SELF-ALIGNED+CONTACT+USING+THE+SAME&rft.inventor=SHIN%2C+GYEONG+SEOP&rft.inventor=LEE%2C+WON+SEOK&rft.inventor=JUNG%2C+SANG+SEOP&rft.date=2001-01-15&rft.externalDBID=B1&rft.externalDocID=KR100275731BB1