PROGRAMMABLE MEMORY ARRAY AND PROGRAMMALE ADDRESS DECODER AND PROGRAMMABLE MUTUAL-CONNECTION CIRCUIT(FIELD PROGRAMMABLE MEMORY ARRAY)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo...

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Bibliographic Details
Main Authors ZITTRISCH, TERRENCE JOHN, CLINTON KIM P.N, GOULD, SCOTT WHITNEY, KEYSER, FRANK RAY 111, KILMOYER, RALPH DAVID, SEIDEL, VICTOR PAUL, IADANZA, JOSEPH ANDREW, LARAMIE, MICHEL JOSEPH
Format Patent
LanguageEnglish
Published 16.10.2000
Edition7
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Summary:A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
Bibliography:Application Number: KR19960046031