DRAM ADDRESS CONTROL METHOD AND DRAM MEMORY STRUCTURE FOR AN RS-CODEC OF A D-VHS

• Main Author: KWON, BONG HYUN
• Format: Patent
• Language: English
• Published: 15.07.2000
• Edition: 7
• Subjects: INFORMATION STORAGE; INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER; PHYSICS

PURPOSE: A method of controlling a DRAM address for RS(Reed-Solomon) CODEC(Coder-Decoder) of a D-VHS(Digital-Video Home System) is provided to efficiently perform read/write processes relating to digital data in a DRAM, to perform a function of the RS CODEC, so that a user can automatically construct an operation environment of a required system. CONSTITUTION: A D-VHS(Digital-Video Home System) inputs a track number and a sync block number of a main code, to write/read digital data in a DRAM. The D-VHS generates an offset row address corresponding to an address allowed to a place where the first byte is recorded, on a track allowed with the inputted track number. The D-VHS adds many upper bits of the sync block number expressed as a binary having many bits, scheduled in the offset row address, and generates an added row address. The D-VHS arranges the added row address to a lower bit direction, and arranges a scheduled binary having one bit as a most significant bit in the added row address, depending on whether the digital data performs write/read processes on tracks with 6 track units, then generates a row address in which the main code is recorded. The D-VHS divides a byte number to the first scheduled value, and generates a share and a remainder. The D-VHS arranges many lower bits of the sync block number to an upper bit direction, and connects a share expressed as the binary to a lower bit direction on the bits of the sync block number, then generates a column address in which the main code is recorded.