CURRENT MEMORY CIRCUIT

• Main Authors: MIN, BYUNG-MOO, CHOI, HUN-BAE
• Format: Patent
• Language: English
• Published: 15.07.2000
• Edition: 7
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PURPOSE: A current memory circuit is provided to output an output signal without a clock feed through delayed an input signal by one period. CONSTITUTION: If an input signal(iin) is inputted, an NMOS transistor is turned on which receives a current adding the input signal and a current(I) of a current source(IS1) through a gate and a drain. Then, if a clock signal(CLK) of a high voltage is applied, PMOS transistors(PM3,PM5) and NMOS transistors(NM2,NM4) are turned on. Next, PMOS transistors(PM4,PM6) are turned on and NMOS transistors(NM3,NM4) are turned on according to the operation of the PMOS transistors(PM3,PM5) and the NMOS transistors(NM2,NM4). Next, an inversion amplifier(2) outputs an output current(io2) by inverting a contact point signal of the PMOS transistor(PM4) and the NMOS transistor(NM3), and the output current(io2) is added with an output current(io1) at a drain of the PMOS transistor(PM6), and a clock feed through by the control of the clock signal is canceled each other, and thus an output signal(iout) has little clock feed through. Next, if the clock signal of a low voltage is inputted, the NMOS transistors(NM2,NM4) and the PMOS transistors(PM3,PM5) are turned off, the current applied to the drain of the NMOS transistors and to the source of the PMOS transistors does not change, but a current applied to the source of the NMOS transistors and to the drain of the PMOS transistors is maintained, and thus the output signal maintains a value when the clock signal of a high voltage is applied. Again, the clock signal of a high voltage is applied, the output signal corresponding to the current value applied to the drain of the NMOS transistors and to the source of the PMOS transistors when the clock signal of a low voltage is applied is output. Accordingly, a current memory outputs the output signal made by delaying the input signal by one period of the clock signal.