NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY CELLS OF PLATE CELL STRUCTURE AND PROGRAM METHOD THEREOF

PURPOSE: An NAND type flash memory device having a plate cell structure is provided to lower a voltage applied to a booster plate when a program is operated. CONSTITUTION: The flash memory device includes a cell array(100), a section decoder(120), a block decoder(110) and a booster plate(102). The c...

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Main Authors JUNG, TAE-SUNG, LEE, DONG-KEE
Format Patent
LanguageEnglish
Published 15.04.2000
Edition7
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Abstract PURPOSE: An NAND type flash memory device having a plate cell structure is provided to lower a voltage applied to a booster plate when a program is operated. CONSTITUTION: The flash memory device includes a cell array(100), a section decoder(120), a block decoder(110) and a booster plate(102). The cell array electrically erasable and programmable memory cells having a source, a drain, a floating gate and a control gate, and a conductive layer covering the memory cells. The section decoder supplies the first voltage to the control gate of a cell being addressed of the memory cells. The block decoder supplies the second voltage to the conductive layer after the control gate of the addressed memory cell is sufficiently charged to the first voltage. When the second voltage is applied to the conductive layer, the booster plate makes it possible doing so that the voltage of the control gate is boosted by the second voltage by cutting that the first voltage is applied to the control gate.
AbstractList PURPOSE: An NAND type flash memory device having a plate cell structure is provided to lower a voltage applied to a booster plate when a program is operated. CONSTITUTION: The flash memory device includes a cell array(100), a section decoder(120), a block decoder(110) and a booster plate(102). The cell array electrically erasable and programmable memory cells having a source, a drain, a floating gate and a control gate, and a conductive layer covering the memory cells. The section decoder supplies the first voltage to the control gate of a cell being addressed of the memory cells. The block decoder supplies the second voltage to the conductive layer after the control gate of the addressed memory cell is sufficiently charged to the first voltage. When the second voltage is applied to the conductive layer, the booster plate makes it possible doing so that the voltage of the control gate is boosted by the second voltage by cutting that the first voltage is applied to the control gate.
Author JUNG, TAE-SUNG
LEE, DONG-KEE
Author_xml – fullname: JUNG, TAE-SUNG
– fullname: LEE, DONG-KEE
BookMark eNqNjb0OgkAQhCm08O8dNrE2Afyrj2ORi3e3ZDlIqAgxZ2XQRJ_F55UYGjuryUzmm5kHk_7e-1nwtmQ3NWnhlEYo0ShJNq2kIwaDhriBFGslEXJRK3sC1CgdKym0bgBZlCIZQGFTKJhOLIz5BiMrUesSKINieMCvhdLxsF_xDzUALqcUXI6MlC2D6bW7Pf1q1EWwztDJfOMf99Y_H93F9_7VnjkKw3gf746HJIm2_7U-xMVFGw
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Physics
Edition 7
ExternalDocumentID KR100252476BB1
GroupedDBID EVB
ID FETCH-epo_espacenet_KR100252476BB13
IEDL.DBID EVB
IngestDate Fri Jul 19 16:35:10 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_KR100252476BB13
Notes Application Number: KR19970019239
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000415&DB=EPODOC&CC=KR&NR=100252476B1
ParticipantIDs epo_espacenet_KR100252476BB1
PublicationCentury 2000
PublicationDate 20000415
PublicationDateYYYYMMDD 2000-04-15
PublicationDate_xml – month: 04
  year: 2000
  text: 20000415
  day: 15
PublicationDecade 2000
PublicationYear 2000
RelatedCompanies SAMSUNG ELECTRONICS CO, LTD
RelatedCompanies_xml – name: SAMSUNG ELECTRONICS CO, LTD
Score 2.5140672
Snippet PURPOSE: An NAND type flash memory device having a plate cell structure is provided to lower a voltage applied to a booster plate when a program is operated....
SourceID epo
SourceType Open Access Repository
SubjectTerms INFORMATION STORAGE
PHYSICS
STATIC STORES
Title NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY CELLS OF PLATE CELL STRUCTURE AND PROGRAM METHOD THEREOF
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000415&DB=EPODOC&locale=&CC=KR&NR=100252476B1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dT8IwsCH4-aao8QNNEw1vi8A2iA-L2bqOIdu6dGOBJ7KOkRgTIDLjP_H3eqsg-sJbe81d02vurtfeXRF6aGZpV-10nxQ1zYWizdQU9CC0hJrqoj3LwOLKaIug4w61l5E-qqC3TS6MrBP6KYsjgkRlIO-F1NfL7SWWLWMrV4_iFUCLZyc27MbGOy7LR-kN2zJoyGxGGoQYA94IuFFWGtXbWrdjgau0B-fobikONLHKtJTlX5vinKD9EMjNi1NUyec1dEQ2X6_V0KG_fvGuoQMZopmtALgWw9UZ-gpAASbMM-O-R3FUspIF9pDEjGOf-oyPsU2TPqHYNZN-0MPUoyQuf3f0vDGm3IxMCxDNwMYhZz1u-r4ErHEJ9bwIMweHMAOVXRzFHOgP-T8sQIhdZuPYpZwy5xzdOzQmrgJLnfwydjLgW7ZYLfUCVeeLeX6JMIBEu5UKMHHgn0xzkeWikzWbGTTFdDq7QvVdlK53D9-g45-Edk1p6XVULd4_8lsw7YW4k1vyDb_mnRE
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dT8IwsCH4gW-KGj9Qm2h4IwLbID4Qs3UdQ7qVlELgiaxjJMZkEMH4T_y93iqIvvDWXnPX9Jq767V3V4QeqnHUNBrNp4oRJapizowI9CC0lBFZqj6LweLqaIuw4Q_Ml5E1yqG3TS6MrhP6qYsjgkTFIO8rra8X20ssV8dWLh_VK4Dmz55sueWNd5yVj7LKrtOiPe5yUiak1RXlULSySqNW3Ww2HHCV9uCM3czEgQ6dLC1l8demeMdovwfk0tUJyiVpERXI5uu1IjoM1i_eRXSgQzTjJQDXYrg8RV8hKMAhZ7bsMIr7GSt56A6I5AIHNOBijF067BCKfXvYCduYMkpk9rsjY2NMhd23HUC0Qxf3BG8LOwg0YI1LKGN9zD3cgxmo7uK-FEB_IP5hAYL0uYulTwXl3hm696gkfgWWOvll7KQrtmxxasY5yqfzNLlAGECqXosUmDjwT6aJihPViKvVGJpqOp1dotIuSle7h-9QwZcBm7BO2L1GRz_J7WalZpVQfvX-kdyAmV-pW709300ToAQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=NON-VOLATILE+SEMICONDUCTOR+MEMORY+DEVICE+HAVING+ELECTRICALLY+ERASABLE+AND+PROGRAMMABLE+MEMORY+CELLS+OF+PLATE+CELL+STRUCTURE+AND+PROGRAM+METHOD+THEREOF&rft.inventor=JUNG%2C+TAE-SUNG&rft.inventor=LEE%2C+DONG-KEE&rft.date=2000-04-15&rft.externalDBID=B1&rft.externalDocID=KR100252476BB1