SEMICONDUCTOR DEVICE

• Main Authors: HORIUCHI, MICHIO, HARAYAMA, YOICHI
• Format: Patent
• Language: English; Korean
• Published: 01.09.1999
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

본 발명은 간단한 구성으로 제조가 용이하고, 저가로 제조할 수 있는 반도체장치에 관한 것으로, 본발명은 반도체칩(32)의 비활성화막(34)상에 이방성도전시트(38)가 배치되고, 상기 이방성도전시트(38)상에 배선패턴(40)이 형성되고, 상기 배선패턴(40)과 상기 반도체칩(32)의 전극(36)이 상기 이방성도전시트(38)가 가압됨으로서 전기적도통이 되고, 상기 이방성도전시트(38) 및 전기배선패턴(40)상에 상기 배선패턴(40)의 외부접속단자접합부(40a)를 노출하여 전기적절연피막(42)이 형성되고, 상기 노출된 외부접속단자접합부(40a)에 외부접속단자(46)가 형성되어 있는 것을 특징으로 한다. A chip sized semiconductor device (30) includes a semiconductor chip (32) having upper and lower surfaces. The chip (32) has electrodes (36) formed on its upper surface. An electrically insulating passivation film (34) is formed on the upper surface of the semiconductor chip (32) except for areas where the electrodes (36) exist. An anisotropic conductive sheet (38) has an upper surface provided with a circuit pattern (40) formed on it and a second surface adhered to the passivation film (34). The circuit pattern (40) has inner and outer connecting portions. An electrically insulating film (42) covers the upper surface of the anisotropic conductive sheet (38) so that the outer connecting portions of the circuit pattern (40) are exposed to be connected to external connecting terminals (46). The anisotropic conductive sheet (38) is partially pressed at positions corresponding to the electrodes (36), so that the inner portions of the circuit pattern (40) are thereby electrically connected to said electrodes (36) of the semiconductor chip (32).