BIT LINE PRECHARGE CIRCUIT

An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line...

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Bibliographic Details
Main Authors BYUN, HYUN-KEUN, KWAK, CHUNG-KEUN, KIM, DOO-WUNG, SEO, YONG-HO
Format Patent
LanguageEnglish
Published 15.04.1999
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.
Bibliography:Application Number: KR19950040996