METHOD OF RELIABILITY TEST FOR SEMICONDUCTOR DEVICE

• Main Authors: BABA ISAO, MAGOME NORIO
• Format: Patent
• Language: English
• Published: 20.03.1989
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE:To prevent a current flowing between a substrate and the outer frame part of a lead frame by a method wherein voltage is applied to a semiconductor element through the intermediary of an inner lead in the state wherein a tag lead is cut off from the outer frame part of the lead frame and it is supported by the outer frame part of the lead frame using a sub-tag lead, and a reliability test is conducted thereon. CONSTITUTION:After a part on the tip side of a sub-tag lead 21 has been molded by resin, a tag lead 5 and an inner lead 9 are cut off at an oblique-lined part 13 in the prescribed width. As a result, a resin-molded part 15 is brought into the state wherein it is supported by the outer frame part 3 of a lead frame by the sub-tag lead 21. In the above-mentioned state, prescribed voltage is applied to each inner lead 9, a semiconductor element is brought into a working state, and a reliability test is conducted. Accordingly, a bed part 7 is brought in the state wherein it is insulated from the outer frame part 3 of the lead frame, and no current flows to the substrate and the outer frame part 3 of the lead frame even when the prescribed back-gate voltage is biased to the substrate of the semiconductor element 1.