POLARITY DECIDING CIRCUIT FOR CONTROLLING LOW FREQUENCY COMPONENT SUPPRESSING INTEGRAL VALUE

• Main Authors: IWAMATSU TAKANORI, AONO YOSHITAMI, TAKENAKA SADAO, MINOWA MORIHIKO
• Format: Patent
• Language: English
• Published: 20.01.1989
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PURPOSE:To reduce the number of hardwares and to simplify and adjust timing by tabulating a part of calculation necessary for generating a polarity signal for a low frequency component suppressing integration restricting value. CONSTITUTION:The sum Si of the i-th frame out of input digital data X(i-1)j is inputted to a memory 151 by a timing signal FRMI through a total adder 10 and an FF 12 and a deviation to be table data for the data of respective frames and mean values and a polarity signal Ci are outputted. The signal Ci is set up in an FF circuit 19 by the succeeding timing signal FRM II. The data of the frame i-1 in a delay buffer 32 are code-converted by a code converter 34 based on the polarity signal Ci-1. On the other hand, the deviation is inputted to a total adder 171 together with data Di-1 stored in an FF circuit group 172 based on a timing signal FRM III and data Di up to the frame (i) are outputted. On the other hand, data Di-1 from the FF 172 are inputted to a memory 151 and the signal Ci corresponding to the Si and Di-1 is outputted. The signal Ci-1 from the FF 19 is inputted to a low frequency component suppressing integral value control circuit part.