DELAY CIRCUIT

PURPOSE:To reduce the number of delay elements and to reduce also the area of a chip by connecting two MOS transistors(TRs) to the output of an inverter circuit to constitute a delay circuit. CONSTITUTION:When a signal impressed to an input terminal is changed from logical value '0' to �...

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Bibliographic Details
Main Author KANO TOSHIYUKI
Format Patent
LanguageEnglish
Published 20.01.1989
Subjects
AMPLIFIERS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:PURPOSE:To reduce the number of delay elements and to reduce also the area of a chip by connecting two MOS transistors(TRs) to the output of an inverter circuit to constitute a delay circuit. CONSTITUTION:When a signal impressed to an input terminal is changed from logical value '0' to '1', a P-MOS-TR 3 is turned off, an N-MOS-TR 5 is turned on and a logical value '0' is outputted from a terminal 4. When the signal impressed to the terminal 1 is changed from the logical value '1' to '0', the TR 3 is turned on and the TR 5 is turned off. At that time, the output of the inverter circuit 2 is changed from the logical value '0' to '1' and the output of the terminal 4 is also changed from the logical value '0' to '1', but the output change of the terminal 4 is delayed only by the sum of the delay time of the circuit 2 and the delay time of the TR 3. Namely, only the signal changing from the logical value '0' to '1' out of signals outputted from the terminal 4 is delayed.
Bibliography:Application Number: JP19870173072