SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To decrease signal wirings necessary for the correction of layouts, and to shorten the time required for the layouts of wirings by conducting fixed potential wirings in a wiring region after the layouts of signal wirings. CONSTITUTION:A plurality of connecting sections on fixed potential wir...

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Bibliographic Details
Main Author TAKECHI MAKOTO
Format Patent
LanguageEnglish
Published 12.04.1988
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Summary:PURPOSE:To decrease signal wirings necessary for the correction of layouts, and to shorten the time required for the layouts of wirings by conducting fixed potential wirings in a wiring region after the layouts of signal wirings. CONSTITUTION:A plurality of connecting sections on fixed potential wirings 13, 14 for a macro cell 7 are formed among one terminals of these wirings and the other terminals, thus connecting wirings 17 or 18 at arbitrary points on the wirings 13 or 14. Consequently, the layouts of fixed potential wirings arranged in a wiring region 12 can be altered variously, thus laying out the fixed potential wirings in the wiring region 12 after the layouts of signal wirings. Accordingly, supply potential wirings and ground potential wirings cannot be wired in the wiring region 12 having the high wiring density of the signal wirings, thus decreasing the number of the signal wirings necessary for the correction of layouts, then shortening the time required for the design of the wirings.
Bibliography:Application Number: JP19860225977